set TOP_MODULE_SRC "N_bit_adder"
# Name of the TOP module in your RTL design source codes.
# For example: set TOP_MODULE_SRC "Your_src_top_module_name"

set TOP_MODULE_SIM "N_bit_adder_tb"
# Name of the TOP module in your RTL simulation codes.
# For example: set TOP_MODULE_SIM "Your_sim_top_module_name"

set SRC_FILELIST {nbit_adder.v}
# A list of source files of your RTL design.
# You can modify this variable to contain all of your RTL codes and initialization files.
# Please separate the different filenames in this line of code with spaces. For example:
# set SRCFILELIST {A.v B.v C.hex D.mem}

set SIM_FILELIST {nbit_adder_tb.v}
# A list of source files of your RTL design.
# You can modify this variable to contain all of your RTL codes and initialization files.
# Please separate the different filenames in this line of code with spaces. For example:
# set SIM_FILELIST {A_tb.v B.mem}

#-------- You can modify codes above this line, but you should modify codes below this line carefully!

set REPORT_DIR "./reports"
# Your report directory.

set SRC_DIR "./src"
# Your RTL design source file directory.

set SIM_DIR "./sim"
# Your RTL design testbench file directory for simulation.

set PROJECT_DIR "./nbit_adder"
# Your Vivado project directory.

set PROJECT_NAME "nbit_adder"
# Vivado project name.

set FPGA_PART "xc7s50csga324-1"
# Part for boolean board.

set SIM_RESULT "simulation_results.log"
# Simulation result filename in testbench.

# Step 0: Initialize

set CLEAN_FILELIST {*.backup.jou *.backup.log *.backup.str}
foreach cleanfile $CLEAN_FILELIST {
    set files [glob -nocomplain ./$cleanfile]
    
    if {[llength $files] == 0} {
        puts "No files found for pattern: $cleanfile"
    } else {
        foreach file $files {
            file delete -force $file
            puts "Deleted file: $file"
        }
    }
}
# These codes delete *backup.jou, *.backup.log and *.backup.str.

set SIMWV_EXTLIST {*.wdb *.vcd *.wcfg *.log}

foreach fileEXT $SIMWV_EXTLIST {
    set files [glob -nocomplain $REPORT_DIR/$fileEXT]
    
    if {[llength $files] == 0} {
        puts "No files found for pattern: $cleanfile"
    }   else {
        foreach file $files {
            file delete -force $file
            puts "Deleted file: $file"
        }
    }
}
# This deletes duplicate files in $REPORT_DIR to facilitate file saving.

set DIRLIST [list $REPORT_DIR $SRC_DIR $SIM_DIR]

foreach dir $DIRLIST {

    if {$dir eq ""} {
        puts "## Error: One of the directory variables is empty. Aborting..."
        exit
    }

    if {![file isdirectory $dir]} {
        if {[catch {file mkdir $dir} result]} {
            puts "## Error: Failed to create directory $dir. Reason: $result"
        } else {
            puts "## Directory $dir created successfully."
        }
    }
}
# This checks the existence of $REPORT_DIR, $SRC_DIR and $SIM_DIR

# Step 1: Create a new project
create_project -force $PROJECT_NAME $PROJECT_DIR -part $FPGA_PART
# This creates a project named nbit_adder in the folder nbit_adder with a specific FPGA part.

# Step 2: Add source files (adder.v and adder_tb.v)
foreach file $SRC_FILELIST {
    add_files -fileset sources_1 $SRC_DIR/${file}
}

update_compile_order -fileset sources_1

foreach file $SIM_FILELIST {
    add_files -fileset sim_1 $SIM_DIR/$file
}
update_compile_order -fileset sim_1

# This adds the Verilog source files to the project. Modify the file paths as needed.

# Step 3: Set the top module for synthesis
set_property top $TOP_MODULE_SRC [get_fileset sources_1]

# Step 4: Set the top module for simulation
set_property top $TOP_MODULE_SIM [get_filesets sim_1]
# This sets the top module to "cla_adder_tb", which is your testbench.

# Step 5: Run simulation using xsim
launch_simulation
# This opens the simulation environment (XSim).

# Step 6: Save VCD waveform data
open_vcd sim_waveform_behav.vcd
# This opens a Value Change Dump (VCD) file for capturing simulation output. 

log_vcd /$TOP_MODULE_SIM
# This logs Value Change Dump (VCD) simulation output for all signals.

run all
# This command runs the simulation till it completes.

close_vcd
# This flushes VCD information to the VCD output file and close the file.

# Step 7: Save WCFG WDB waveform data
save_wave_config $REPORT_DIR/sim_waveform_behav.wcfg
# This saves the waveform config to a file for later viewing.

# Step 8: Stop simulation
stop
# This stops the simulation process.

close_sim 
# This closes Xsim.

file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/behav/xsim/${TOP_MODULE_SIM}_behav.wdb $REPORT_DIR/sim_waveform_behav.wdb
# This saves the waveform data to a file for later viewing.

file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/behav/xsim/$SIM_RESULT $REPORT_DIR/sim_results_behav.log
# This saves the simulation output log file.

# file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/behav/xsim/sim_waveform_behav.vcd $REPORT_DIR
# This saves the waveform value change dump file(.vcd) to a file for later viewing.

# Step 9: Run synthesis
launch_runs synth_1
# This runs the synthesis step for the design.

# Step 10: Wait for synthesis to complete
wait_on_run synth_1
# This waits for the synthesis to complete before continuing.

launch_simulation -mode post-synthesis -type timing

open_vcd sim_waveform_time_synth.vcd
# This opens a Value Change Dump (VCD) file for capturing simulation output. 

log_vcd /$TOP_MODULE_SIM
# This logs Value Change Dump (VCD) simulation output for all signals.

run all
# This command runs the simulation till it completes.

close_vcd

save_wave_config $REPORT_DIR/sim_waveform_time_synth.wcfg
# This saves the waveform config to a file for later viewing.

# Step 8: Stop simulation
stop
# This stops the simulation process.

close_sim 
# This closes Xsim.

file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/synth/timing/xsim/${TOP_MODULE_SIM}_time_synth.wdb $REPORT_DIR/sim_waveform_time_synth.wdb
# This saves the waveform data to a file for later viewing.

file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/synth/timing/xsim/$SIM_RESULT $REPORT_DIR/sim_results_time_synth.log
# This saves the simulation output log file.

# file copy $PROJECT_DIR/${PROJECT_NAME}.sim/sim_1/synth/timing/xsim/sim_waveform_time_synth.vcd $REPORT_DIR
# This saves the waveform value change dump file(.vcd) to a file for later viewing.

# Step 11: Export synthesis reports
open_run synth_1
report_utilization -file $REPORT_DIR/utilization_report.rpt
report_timing_summary -file $REPORT_DIR/timing_report.rpt
# These commands export the utilization report and the timing summary report.

# Optional Step: If you want to export the synthesized design netlist (optional)
# write_checkpoint -force $REPORT_DIR/adder_synth.dcp
# This exports the synthesized netlist to a DCP (Design Checkpoint) file.

# The implementation (layout and routing) is not included because you don't have XDC constraints.

exit